A typical high voltage NMOS device 10 (FIG. 1), normally one of a large grid of cells, includes a P- substrate 12 having an N- epitaxial layer 14 thereover, the substrate 12 and epitaxial layer 14 together making up the body 16 of the device 10. An N+ buried layer 18 is shown at the junction of the epitaxial layer 14 and substrate 12. A boron P- well 20 (the "Pwell") is formed in the epitaxial layer 14, and formed in the Pwell 20 are the N type source 22 and drain 24 of the device 10. The drain 24 is made up of a heavily doped main region 26 and a lightly doped extended region 28. Doping of the source 22 and drain 24 may be by, for example, arsenic or phosphorus. A gate oxide 30 and a gate 32 are included, and contacts 34, 36 reach to the source 22 and drain 24 respectively, through a dielectric layer such as oxide layer 38.
Several failure mechanisms which are competitive in nature limit the maximum operating voltage of the device 10. These mechanisms can be summarized as follows:
1. The intrinsic breakdown voltage of the drain/Pwell junction is determined by the dopant concentrations on each side of the junction, and their gradients. The lower the dopant concentration on each side and the more gradual the increase in concentration away from the junction, the higher the breakdown voltage of the device. However, lower dopant concentration on the drain side (especially the extended region 28) increases the ON-resistance of the device. Lower dopant concentration on the Pwell side, on the other hand, may cause premature punchthrough of the parasitic vertical NPN bipolar transistor made up of drain 24, Pwell 20, and the epitaxial layer 14 and buried layer 18 N regions. This intrinsic breakdown voltage may undesirably be further lowered due to high electric fields at the curved regions of the junctions or at the oxide/silicon surface.
2. High electric fields at the surface 40 of the body 16 may rupture the oxide 30 at the drain edge. The magnitude of the electric field at the surface 40 is a function of the length of the extended drain region 28 (indicated at X) as well as the dopant concentration in that region. Lower dopant concentration and longer extension length insure a lower surface field but at the expense of larger device size and higher on-resistance.
3. At higher voltages, the drain/Pwell depletion region further extends into the Pwell 20 causing parasitic vertical NPN bipolar device punchthrough. High Pwell concentration increases the punchthrough voltage, but with the breakdown voltage of the device being lowered.
Alternatively, the device can be built on a buried layer 18 that is the same conductivity as the substrate 12 (for example P+ in FIG. 1) so that the problem of punchthrough is avoided, but with the breakdown problem remaining.
FIGS. 2-6 illustrate the process steps for fabricating the device of FIG. 1. With reference to FIG. 2, the device as thus far fabricated includes a P- type semiconductor substrate 50 with an N- epitaxial layer 52 formed thereover, the substrate 50 and epitaxial layer 52 together making up the body 54 of the device. An N+ buried layer 56 is formed at the junction of the epitaxial layer 52 and substrate 50. A P- well 58 ("Pwell") is formed in the epitaxial layer 52 by implantation and drivein of boron, the Pwell 58 extending to the surface of the epitaxial layer 52. A thin layer of oxide 60 is formed over the surface of the epitaxial layer 52, extending to field oxide regions 62. A polysilicon gate 64 is formed over the oxide.
At this point (FIG. 2) a low dosage of phosphorus 66 is implanted through the thin oxide layer 60 into a Pwell 58 in epitaxial layer 52, the gate 64 and oxide regions 62 forming a mask for such implantation. Subsequent thermal processing causes the phosphorus 66 to diffuse into the Pwell 58, forming the regions 68, 70 shown in FIG. 3. Then, a layer of oxide 72 is deposited on the resulting structure (FIG. 4). An anisotropic etch is undertaken to define oxide spacers 74 (FIG. 5).
Photoresist 76 is then applied and patterned as shown in FIG. 5, and a high dosage of phosphorus 78 is implanted as shown. After removal of the photoresist 76, diffusion of the phosphorus 78 is undertaken to form the device of FIG. 6, including source 80 and drain 82, which drain 82 includes heavily doped region 84. As shown therein, the dimension X indicates the length of the lightly doped extended drain region 86, extending from the heavily doped main drain region 84 toward the source 80, so that channel region 88 is defined between the source 80 and the extended drain region 86.
As an alternative, a like process flow incorporating arsenic in place of phosphorus to form the source and drain is also commonly used. Completion of the process results in the device of FIG. 1.
Doping profiles in the drain/Pwell region as indicated at section I--I of FIG. 6 are illustrated in FIG. 7, for phosphorus implanted at 7E12 cm.sup.-2 at 60 KeV to form the extended drain region or arsenic implanted at 7E12 cm.sup.-2 at 120 KeV to form the extended drain region, with different thermal cycles to yield approximately the same or similar junction depths. Corresponding one-dimensional intrinsic breakdown voltages of these Pwell-extended drain region junctions are 29.3 volts and 28.9 volts for phosphorus and arsenic process flows respectively. However, measurements of these devices indicate failure at 23 volts due to punchthrough.
Increasing the Pwell boron dose and/or drivein time will result in a higher punchthrough voltage in each (i.e., phosphorus or arsenic type) device. FIG. 8 illustrates simulated punchthrough/breakdown voltage tradeoffs as a function of Pwell drive time for three different Pwell doses (7E12 cm.sup.-2, 6E12 cm.sup.-2, and 5E12 cm.sup.-2, all at 80 KeV), with drivein undertaken at 1100.degree. C.
For a specific application, a breakdown voltage higher than 25 volts and a punchthrough voltage higher than 30 volts are required. With reference to FIG. 8, a 5E12 cm.sup.-2 Pwell dose is shown to be inadequate, regardless of the Pwell drive time, to meet the punchthrough voltage requirement, although a high breakdown voltage would be provided. As the Pwell dose is increased to 6E12 cm.sup.-2, especially with increased Pwell drive time, the device seems to meet both the breakdown and punchthrough specifications. These numbers, however, represent one-dimensional simulation results under nominal processing conditions. Two-dimensional breakdown mechanisms, as well as process variations, easily lower either the breakdown or punchthrough voltage. Increasing the Pwell dose to 7E12 cm.sup.-2 to increase the punchthrough voltage, however, reduces the breakdown voltage as indicated in FIG. 8.
As an alternative, all conductivities of the device can be reversed, with the same analysis applying.
Reference is made to "An As-P(n.sup.+ -n.sup.-) Double Diffused Drain MOSFET for VLSI's," by Eiji Takeda, IEEE Transactions On Electron Devices, Vol. ED-30, No. 6, Jun. 19, 1983 IEEE, which discusses a double diffused drain MOSFET device. In such a device, phosphorus is implanted into the mask device body and diffused thereinto, and subsequently, using the same mask, arsenic is implanted into the body to combine with phosphorus to form the source and drain of the device. However, it will be noted that this document is not concerned with high voltage devices or with extended drain regions and drain series resistance is not a primary factor.
The article "Profiled Lightly Doped Drain (PLDD) Structure for High Reliable NMOS-FETs," by Y. Toyoshima et al., Semiconductor Device Engineering Laboratory TOSHIBA Corporation, discusses formation of a profiled lightly doped drain of an NMOS device. Both arsenic and phosphorus are used to form the profiled portion of the drain region. However, again, this document is not concerned with a high voltage device, nor is an extended drain region formed of the type utilized in a high voltage device. Both articles are concerned with improving the reliability of low-voltage NMOS.